| { |
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| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| "min_pulse_width_low": 0.09577, |
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| }, |
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| "clock_gate_enable_pin": "true", |
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| }, |
| "pin,GCLK": { |
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| "direction": "output", |
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| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
