| { |
| "area": 23.976, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01324, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.71979, |
| "min_pulse_width_low": 0.71979, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.0027, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| 0.0042 |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.05751, |
| 0.33179, |
| 0.38748, |
| 0.45504, |
| 0.53611, |
| 0.63224, |
| 0.74893, |
| 0.8892, |
| 1.05591, |
| 1.25879, |
| 1.50299 |
| ], |
| [ |
| 0.05759, |
| 0.33188, |
| 0.38729, |
| 0.4545, |
| 0.53509, |
| 0.63246, |
| 0.7489, |
| 0.88933, |
| 1.057, |
| 1.25787, |
| 1.50275 |
| ], |
| [ |
| 0.05764, |
| 0.33213, |
| 0.38764, |
| 0.45503, |
| 0.53564, |
| 0.63233, |
| 0.74899, |
| 0.88926, |
| 1.05698, |
| 1.25779, |
| 1.5021 |
| ], |
| [ |
| 0.05888, |
| 0.33226, |
| 0.38795, |
| 0.45472, |
| 0.5357, |
| 0.63218, |
| 0.74832, |
| 0.8883, |
| 1.0562, |
| 1.2578, |
| 1.5024 |
| ], |
| [ |
| 0.06143, |
| 0.3333, |
| 0.3888, |
| 0.4557, |
| 0.536, |
| 0.6327, |
| 0.7484, |
| 0.8884, |
| 1.0564, |
| 1.2576, |
| 1.5021 |
| ], |
| [ |
| 0.065, |
| 0.3359, |
| 0.391, |
| 0.4575, |
| 0.5376, |
| 0.6342, |
| 0.7494, |
| 0.8898, |
| 1.0577, |
| 1.2579, |
| 1.5009 |
| ], |
| [ |
| 0.0705, |
| 0.3379, |
| 0.3928, |
| 0.4593, |
| 0.5396, |
| 0.6356, |
| 0.7514, |
| 0.8918, |
| 1.0591, |
| 1.2605, |
| 1.5022 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
