| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01239, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| }, |
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| "min_pulse_width_low": 0.54401, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
| "max_transition": 1.0, |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| [ |
| 0.052, |
| 0.0976, |
| 0.106, |
| 0.1162, |
| 0.1285, |
| 0.1432, |
| 0.1608, |
| 0.1824, |
| 0.2082, |
| 0.2393, |
| 0.2774, |
| 0.324, |
| 0.3787, |
| 0.4456, |
| 0.5267, |
| 0.6248, |
| 0.7425, |
| 0.884, |
| 1.0538, |
| 1.2577, |
| 1.5037 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
