| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01238, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_low": 0.45612, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| }, |
| "max_transition": 1.0, |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
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| }, |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.08049, |
| 0.08668, |
| 0.0941, |
| 0.10287, |
| 0.11327, |
| 0.12571, |
| 0.14051, |
| 0.15826, |
| 0.17983, |
| 0.20561, |
| 0.23711, |
| 0.2749, |
| 0.32095, |
| 0.37612, |
| 0.44374, |
| 0.52455, |
| 0.62282, |
| 0.74072, |
| 0.88098, |
| 1.05138, |
| 1.25713, |
| 1.50146 |
| ], |
| [ |
| 0.04542, |
| 0.08055, |
| 0.08681, |
| 0.09415, |
| 0.10283, |
| 0.11327, |
| 0.12571, |
| 0.14061, |
| 0.15827, |
| 0.17987, |
| 0.20566, |
| 0.23713, |
| 0.27479, |
| 0.32085, |
| 0.37667, |
| 0.44398, |
| 0.52482, |
| 0.62274, |
| 0.74095, |
| 0.88151, |
| 1.05194, |
| 1.25702, |
| 1.50064 |
| ], |
| [ |
| 0.04546, |
| 0.08057, |
| 0.0868, |
| 0.09416, |
| 0.10302, |
| 0.1133, |
| 0.12584, |
| 0.14066, |
| 0.15829, |
| 0.17993, |
| 0.20578, |
| 0.23712, |
| 0.27505, |
| 0.3206, |
| 0.37606, |
| 0.44316, |
| 0.52463, |
| 0.62287, |
| 0.74016, |
| 0.88199, |
| 1.05174, |
| 1.25589, |
| 1.50308 |
| ], |
| [ |
| 0.04561, |
| 0.08056, |
| 0.08695, |
| 0.09443, |
| 0.10304, |
| 0.11353, |
| 0.12597, |
| 0.14081, |
| 0.1585, |
| 0.17997, |
| 0.20598, |
| 0.23727, |
| 0.2748, |
| 0.32103, |
| 0.3765, |
| 0.44402, |
| 0.52467, |
| 0.62197, |
| 0.74055, |
| 0.8814, |
| 1.05131, |
| 1.25686, |
| 1.5025 |
| ], |
| [ |
| 0.04723, |
| 0.08154, |
| 0.0879, |
| 0.09515, |
| 0.10382, |
| 0.11418, |
| 0.12655, |
| 0.14134, |
| 0.15898, |
| 0.18052, |
| 0.20623, |
| 0.2374, |
| 0.27543, |
| 0.32109, |
| 0.37641, |
| 0.44362, |
| 0.52504, |
| 0.62391, |
| 0.73966, |
| 0.8827, |
| 1.0516, |
| 1.2556, |
| 1.5021 |
| ], |
| [ |
| 0.05102, |
| 0.0857, |
| 0.0919, |
| 0.099, |
| 0.1076, |
| 0.1178, |
| 0.13, |
| 0.1445, |
| 0.1617, |
| 0.1829, |
| 0.2084, |
| 0.2391, |
| 0.2767, |
| 0.3224, |
| 0.3771, |
| 0.4445, |
| 0.5247, |
| 0.6229, |
| 0.7412, |
| 0.8828, |
| 1.0526, |
| 1.2566, |
| 1.5025 |
| ], |
| [ |
| 0.0564, |
| 0.0913, |
| 0.0976, |
| 0.1049, |
| 0.1133, |
| 0.1234, |
| 0.1354, |
| 0.1498, |
| 0.1671, |
| 0.1878, |
| 0.2129, |
| 0.2432, |
| 0.2803, |
| 0.3249, |
| 0.3797, |
| 0.4463, |
| 0.5272, |
| 0.6238, |
| 0.742, |
| 0.8822, |
| 1.0518, |
| 1.2572, |
| 1.5008 |
| ], |
| [ |
| 0.0649, |
| 0.0999, |
| 0.1059, |
| 0.113, |
| 0.1215, |
| 0.1312, |
| 0.1432, |
| 0.1572, |
| 0.174, |
| 0.1945, |
| 0.2194, |
| 0.2493, |
| 0.2858, |
| 0.3302, |
| 0.3839, |
| 0.4496, |
| 0.5292, |
| 0.6255, |
| 0.7424, |
| 0.8833, |
| 1.0532, |
| 1.2574, |
| 1.504 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
