| { | |
| "area": 25.5744, | |
| "cell_footprint": "sdlclkp", | |
| "cell_leakage_power": 0.0, | |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin CLK": { | |
| "capacitance": 0.01226, | |
| "clock": "true", | |
| "clock_gate_clock_pin": "true", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
| "index_1": [ | |
| 0.001, | |
| 0.00617, | |
| 0.01028, | |
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| 0.03085, | |
| 0.05553, | |
| 0.09255, | |
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| 0.49977, | |
| 0.83295, | |
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| 1.5 | |
| ], | |
| "values": [ | |
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| 0.02013, | |
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| 0.02111, | |
| 0.02463, | |
| 0.0276, | |
| 0.03303, | |
| 0.03659 | |
| ] | |
| }, | |
| "rise_power hidden_pwr_template13": { | |
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| 0.001, | |
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| ], | |
| "values": [ | |
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| 0.01273, | |
| 0.01174, | |
| 0.013, | |
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| 0.01296, | |
| 0.01316, | |
| 0.01588, | |
| 0.01889, | |
| 0.02393, | |
| 0.0277 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.0, | |
| "min_pulse_width_high": 0.12507, | |
| "min_pulse_width_low": 0.12507, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin GATE": { | |
| "capacitance": 0.00201, | |
| "clock": "false", | |
| "clock_gate_enable_pin": "true", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| 0.001, | |
| 0.00617, | |
| 0.01028, | |
| 0.01851, | |
| 0.03085, | |
| 0.05553, | |
| 0.09255, | |
| 0.16659, | |
| 0.27765, | |
| 0.49977, | |
| 0.83295, | |
| 1.16647, | |
| 1.5 | |
| ], | |
| "values": [ | |
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| 0.0118, | |
| 0.01376, | |
| 0.01237, | |
| 0.0122, | |
| 0.01149, | |
| 0.01158, | |
| 0.01197, | |
| 0.0126, | |
| 0.0153, | |
| 0.01796, | |
| 0.02249, | |
| 0.02576 | |
| ] | |
| }, | |
| "rise_power hidden_pwr_template13": { | |
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| 0.01028, | |
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| 0.03085, | |
| 0.05553, | |
| 0.09255, | |
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| 0.27765, | |
| 0.49977, | |
| 0.83295, | |
| 1.16647, | |
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| ], | |
| "values": [ | |
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| 0.0034, | |
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| 0.00229, | |
| 0.00251, | |
| 0.00324, | |
| 0.00523, | |
| 0.00819, | |
| 0.01221, | |
| 0.01572 | |
| ] | |
| } | |
| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "timing": [ | |
| { | |
| "fall_constraint sethold_template_fall10x10": { | |
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| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
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| ], | |
| "index_2": [ | |
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| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
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| ], | |
| "values": [ | |
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| 0.16431, | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| 0.302, | |
| 0.31372, | |
| 0.32837, | |
| 0.34595, | |
| 0.36353 | |
| ], | |
| [ | |
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| 0.4104, | |
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| ], | |
| [ | |
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| 0.45142, | |
| 0.469, | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| 0.54517, | |
| 0.55689, | |
| 0.57446, | |
| 0.59204 | |
| ] | |
| ] | |
| }, | |
| "related_pin": "CLK", | |
| "rise_constraint sethold_template_rise10x10": { | |
| "index_1": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "index_2": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "values": [ | |
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| 0.08228, | |
| 0.07935, | |
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| 0.09985, | |
| 0.12036, | |
| 0.1438, | |
| 0.17017, | |
| 0.1936 | |
| ], | |
| [ | |
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| 0.08814, | |
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| 0.12622, | |
| 0.14966, | |
| 0.1731, | |
| 0.19946 | |
| ], | |
| [ | |
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| 0.094, | |
| 0.094, | |
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| 0.15845, | |
| 0.18189, | |
| 0.20532 | |
| ], | |
| [ | |
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| 0.16724, | |
| 0.19067, | |
| 0.21704 | |
| ], | |
| [ | |
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| ], | |
| [ | |
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| 0.15552, | |
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| 0.20239, | |
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| ], | |
| [ | |
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| 0.1731, | |
| 0.19653, | |
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| [ | |
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| [ | |
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| 0.12329, | |
| 0.14673, | |
| 0.1731, | |
| 0.19946 | |
| ], | |
| [ | |
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| 0.10864, | |
| 0.13208, | |
| 0.15552, | |
| 0.18189 | |
| ] | |
| ] | |
| }, | |
| "timing_type": "setup_rising" | |
| }, | |
| { | |
| "fall_constraint sethold_template_fall10x10": { | |
| "index_1": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "index_2": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "values": [ | |
| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| [ | |
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| -0.3103, | |
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| ], | |
| [ | |
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| [ | |
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| -0.47436, | |
| -0.49194 | |
| ] | |
| ] | |
| }, | |
| "related_pin": "CLK", | |
| "rise_constraint sethold_template_rise10x10": { | |
| "index_1": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "index_2": [ | |
| 0.01, | |
| 0.03125, | |
| 0.0625, | |
| 0.125, | |
| 0.25, | |
| 0.5, | |
| 0.75, | |
| 1.0, | |
| 1.25, | |
| 1.5 | |
| ], | |
| "values": [ | |
| [ | |
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| 0.01489, | |
| 0.01782, | |
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| 0.01196, | |
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| -0.04663, | |
| -0.073, | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| ], | |
| [ | |
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| [ | |
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| [ | |
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| ], | |
| [ | |
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| [ | |
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| [ | |
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| ] | |
| ] | |
| }, | |
| "timing_type": "hold_rising" | |
| } | |
| ] | |
| }, | |
| "pin GCLK": { | |
| "clock_gate_out_pin": "true", | |
| "direction": "output", | |
| "internal_power": { | |
| "fall_power pwr_template13x18": { | |
| "index_1": [ | |
| 0.001, | |
| 0.00617, | |
| 0.01028, | |
| 0.01851, | |
| 0.03085, | |
| 0.05553, | |
| 0.09255, | |
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| 0.27765, | |
| 0.49977, | |
| 0.83295, | |
| 1.16647, | |
| 1.5 | |
| ], | |
| "index_2": [ | |
| 0.0, | |
| 0.00853, | |
| 0.01066, | |
| 0.01333, | |
| 0.01666, | |
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| 0.15508, | |
| 0.19385, | |
| 0.24231, | |
| 0.30289 | |
| ], | |
| "values": [ | |
| [ | |
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| "timing_sense": "positive_unate" | |
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| }, | |
| "pin M0": { | |
| "direction": "internal", | |
| "internal_node": "m0", | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
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| "clock": "false", | |
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| "direction": "input", | |
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| { | |
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