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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_lp / e35e60066797bc379d0c9007666c6e53a2493d94 / . / cells / sdfsbp / sky130_fd_sc_lp__sdfsbp_lp__ff_150C_2v05.lib.json
blob: 5722b3f8c704c9abe3310781e615af3cee575b5b [file] [log] [blame]
{
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"cell_footprint": "sdfsbp",
"cell_leakage_power": 0.0,
"ff IQ,IQ_N": {
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"next_state": "(D&!SCE) | (SCD&SCE)",
"preset": "!SET_B"
},
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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},
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},
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
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[
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]
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
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0.25,
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1.25,
1.5
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},
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}
]
},
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"clock": "false",
"direction": "input",
"internal_power": {
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0.00617,
0.01028,
0.01851,
0.03085,
0.05553,
0.09255,
0.16659,
0.27765,
0.49977,
0.83295,
1.16647,
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0.04473,
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0.01389,
0.01152,
0.01371,
0.01371,
0.01368,
0.01481,
0.01481,
0.01593,
0.01593
]
},
"rise_power hidden_pwr_template13": {
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0.00617,
0.01028,
0.01851,
0.03085,
0.05553,
0.09255,
0.16659,
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0.49977,
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],
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0.01357,
0.01344,
0.0134,
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0.01576,
0.01576
]
}
},
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"timing": [
{
"related_pin": "CLK",
"rise_constraint rr_template10x10": {
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0.01,
0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
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]
},
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},
{
"related_pin": "CLK",
"rise_constraint rr_template10x10": {
"index_1": [
0.01,
0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
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0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
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0.34276,
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],
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]
]
},
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}
]
},
"test_cell": {
"ff IQ,IQ_N": {
"clocked_on": "CLK",
"next_state": "D",
"preset": "!SET_B"
},
"pin CLK": {
"direction": "input",
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR"
},
"pin D": {
"direction": "input",
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR"
},
"pin Q": {
"direction": "output",
"function": "IQ",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"signal_type": "test_scan_out"
},
"pin Q_N": {
"direction": "output",
"function": "IQ_N",
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"signal_type": "test_scan_out_inverted"
},
"pin SCD": {
"direction": "input",
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"signal_type": "test_scan_in"
},
"pin SCE": {
"direction": "input",
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR",
"signal_type": "test_scan_enable"
},
"pin SET_B": {
"direction": "input",
"max_transition": 1.0,
"related_ground_pin": "VGND",
"related_power_pin": "VPWR"
}
}
}