{
  "area": 27.1728,
  "cell_footprint": "dlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge",
  "dont_use": "true",
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.01217,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "internal_power": {
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          0.02602,
          0.03903,
          0.05855,
          0.08782,
          0.13172,
          0.19757,
          0.29634,
          0.44449,
          0.6667,
          1.0,
          1.5
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        "values": [
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          0.01331,
          0.01291,
          0.01276,
          0.01257,
          0.01278,
          0.01274,
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          0.01367,
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          0.01453,
          0.01445
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.00861,
          0.00851,
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    },
    "max_transition": 1.0,
    "min_pulse_width_high": 0.62604,
    "min_pulse_width_low": 0.62604,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin GATE": {
    "capacitance": 0.00182,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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          0.00174,
          0.00199,
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          0.00199,
          0.00214,
          0.00216,
          0.00231,
          0.00231
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.00196,
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          0.00194,
          0.00214,
          0.00212,
          0.00229,
          0.0023
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      }
    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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            0.0625,
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            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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            0.25,
            0.5,
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            1.5
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              0.14822
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            [
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              0.6785,
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              0.50565,
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            [
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              0.93631,
              0.84842
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        },
        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            1.5
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          "index_2": [
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            0.25,
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            1.5
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        "timing_type": "setup_rising"
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      {
        "fall_constraint sethold_template_fall10x10": {
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            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "index_2": [
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            0.25,
            0.5,
            0.75,
            1.0,
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            1.5
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          "values": [
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              -0.04221,
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              0.07791,
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              0.29471,
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              -0.3176,
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              -0.45822,
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              -0.21799,
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              -0.02463,
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              -0.59885,
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              -0.08322,
              -0.00412
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        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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          "values": [
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              0.17752,
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        "timing_type": "hold_rising"
      }
    ]
  },
  "pin GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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        "index_2": [
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          0.16109,
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        "values": [
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    "internal_node": "m0",
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  "statetable \"CLK GATE\",\"M0\"": {
    "table": "L L : - : L ,L H : - : H ,H - : - : N"
  }
}