{
  "area": 27.1728,
  "cell_footprint": "dfxtp",
  "cell_leakage_power": 0.0,
  "dont_touch": "true",
  "dont_use": "true",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.00201,
    "clock": "true",
    "direction": "input",
    "internal_power": {
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          0.13172,
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          0.44449,
          0.6667,
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          1.5
        ],
        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "min_pulse_width_high": 0.55573,
    "min_pulse_width_low": 0.55573,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin D": {
    "capacitance": 0.00152,
    "clock": "false",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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          0.01176,
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          0.01261,
          0.01256
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.00892
        ]
      }
    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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            0.5,
            0.75,
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              0.78516
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        "related_pin": "CLK",
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        "timing_type": "setup_rising"
      },
      {
        "fall_constraint sethold_template_fall10x10": {
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            0.75,
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            0.75,
            1.0,
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        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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        "timing_type": "hold_rising"
      }
    ]
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  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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      "related_pin": "CLK",
      "rise_power pwr_template13x15": {
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