| { |
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| "cell_footprint": "sky130_fd_sc_lp__sdlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
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| "physical_connection": "device_layer", |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| }, |
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| "clock_gate_enable_pin": "true", |
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| }, |
| "pin,GCLK": { |
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| 0.01898, |
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| ], |
| [ |
| 0.03656, |
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| 0.03656, |
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| -0.0777, |
| -0.10699, |
| -0.13629 |
| ], |
| [ |
| 0.06, |
| 0.06293, |
| 0.06293, |
| 0.05707, |
| 0.03949, |
| 0.00433, |
| -0.03082, |
| -0.06305, |
| -0.09528, |
| -0.1275 |
| ] |
| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
