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| "cell_footprint": "sky130_fd_sc_lp__sdlclkp", | |
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| "clock_gating_integrated_cell": "latch_posedge_precontrol", | |
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| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
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| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
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| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
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| "direction": "input", | |
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| }, | |
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