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  "cell_footprint": "sky130_fd_sc_lp__dlclkp",
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  "clock_gating_integrated_cell": "latch_posedge",
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            0.26732,
            0.3145,
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            0.52188,
            0.62026,
            0.73995,
            0.88105,
            1.0511,
            1.25781,
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          [
            0.03606,
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          [
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            0.31482,
            0.37163,
            0.43991,
            0.52202,
            0.62074,
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            0.88243,
            1.05391,
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            1.50198
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          [
            0.03617,
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            0.37188,
            0.44043,
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          [
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            0.31469,
            0.37157,
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            0.88069,
            1.05148,
            1.25633,
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          [
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            0.31464,
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          [
            0.04012,
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            0.2295,
            0.2684,
            0.3154,
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            0.4402,
            0.5222,
            0.6209,
            0.7394,
            0.882,
            1.051,
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          ],
          [
            0.0434,
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            0.3168,
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            0.4408,
            0.5229,
            0.6215,
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          ],
          [
            0.0481,
            0.1753,
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            0.2714,
            0.3185,
            0.3743,
            0.4417,
            0.5229,
            0.6209,
            0.7391,
            0.8812,
            1.0512,
            1.2563,
            1.5035
          ]
        ]
      },
      "timing_sense": "positive_unate"
    }
  },
  "pin,M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "statetable,CLK GATE,M0": {
    "table": [
      "L L : - : L",
      "L H : - : H",
      "H - : - : N"
    ]
  }
}