tree 5ddbe6c20a9f69f04e5651c440bd76b5530d8258
parent 5b95d7fa72b38163c9b5b96c131d35237c67ac38
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>