)]}'
{
  "commit": "9d1b5257cf0440540926107ddb19a3079ce02de2",
  "tree": "a91b06780f0843f04f252ce9c37fd9e337ffc728",
  "parents": [
    "8b3864a7fd6f2e5a6660534a4c702c2ef1921fff",
    "5b95d7fa72b38163c9b5b96c131d35237c67ac38"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing include path.\n\nThe include lines previously had,\n`include \"sky130_fd_sc_hd__o221a.pp.functional.v\"`\nbut the actual filename is\n`include \"sky130_fd_sc_hd__o221a.functional.pp.v\"`.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}