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| "ff,IQ,IQ_N": { |
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| "next_state": "(D&!SCE) | (SCD&SCE)", |
| "preset": "!SET_B" |
| }, |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
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| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "min_pulse_width_low": 0.54987, |
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| "related_power_pin": "VPWR" |
| }, |
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| "nextstate_type": "data", |
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| }, |
| "pin,Q": { |
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| "function": "IQ", |
| "internal_power": [ |
| { |
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| }, |
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| "direction": "input", |
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| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| "rise_constraint,rr_template10x10": { |
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| }, |
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| }, |
| { |
| "related_pin": "CLK", |
| "rise_constraint,rr_template10x10": { |
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| ] |
| }, |
| "timing_type": "removal_rising" |
| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D", |
| "preset": "!SET_B" |
| }, |
| "pin,CLK": { |
| "direction": "input", |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,D": { |
| "direction": "input", |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "signal_type": "test_scan_enable" |
| }, |
| "pin,SET_B": { |
| "direction": "input", |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| } |
| } |
| } |
