tree 863705935aa5ff52f7fdfbd58188ae98b19bd505
parent 9d32f7b11b25243603baf558eec2ff7f0353c915
parent 37fac29d86a9b340bb679e5dd5e00f5a34d06b21
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>