)]}'
{
  "commit": "8cd81a6e4b2c8863e2dd7cea9219de3046697f5c",
  "tree": "863705935aa5ff52f7fdfbd58188ae98b19bd505",
  "parents": [
    "9d32f7b11b25243603baf558eec2ff7f0353c915",
    "37fac29d86a9b340bb679e5dd5e00f5a34d06b21"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}