{
  "area": 27.1728,
  "cell_footprint": "sdlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge_precontrol",
  "dont_use": "true",
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.01223,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "internal_power": {
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          0.02602,
          0.03903,
          0.05855,
          0.08782,
          0.13172,
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          0.29634,
          0.44449,
          0.6667,
          1.0,
          1.5
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        "values": [
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          0.01257,
          0.01259,
          0.01298,
          0.0121,
          0.01237,
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          0.01299,
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          0.01394,
          0.0139
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.00835
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    "max_transition": 1.0,
    "min_pulse_width_high": 0.46198,
    "min_pulse_width_low": 0.46198,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin GATE": {
    "capacitance": 0.00205,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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          0.00807,
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.00151
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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            0.5,
            0.75,
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            1.25,
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        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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            0.5,
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            1.0,
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            1.0,
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        "timing_type": "setup_rising"
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      {
        "fall_constraint sethold_template_fall10x10": {
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            0.5,
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            1.0,
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            0.5,
            0.75,
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          "values": [
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              -0.29753,
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        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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          "values": [
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        "timing_type": "hold_rising"
      }
    ]
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  "pin GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
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        "values": [
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            ]
          ]
        },
        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
          "index_1": [
            0.01,
            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
          ],
          "index_2": [
            0.01,
            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
          ],
          "values": [
            [
              0.07161,
              0.08039,
              0.09504,
              0.11262,
              0.14192,
              0.18586,
              0.22395,
              0.25618,
              0.28254,
              0.30891
            ],
            [
              0.06282,
              0.07161,
              0.08332,
              0.1009,
              0.1302,
              0.17707,
              0.21223,
              0.24446,
              0.27375,
              0.30012
            ],
            [
              0.04817,
              0.05696,
              0.06868,
              0.08918,
              0.11555,
              0.16243,
              0.19758,
              0.22981,
              0.25911,
              0.28547
            ],
            [
              0.01887,
              0.02766,
              0.03938,
              0.05989,
              0.08625,
              0.13313,
              0.17121,
              0.20344,
              0.22981,
              0.25618
            ],
            [
              -0.03972,
              -0.028,
              -0.01629,
              0.00129,
              0.03059,
              0.07747,
              0.11262,
              0.14485,
              0.17414,
              0.20051
            ],
            [
              -0.14519,
              -0.13347,
              -0.12175,
              -0.09832,
              -0.07195,
              -0.02507,
              0.01301,
              0.04524,
              0.07454,
              0.1009
            ],
            [
              -0.23308,
              -0.22136,
              -0.20964,
              -0.18621,
              -0.15691,
              -0.11003,
              -0.07488,
              -0.04265,
              -0.01336,
              0.01301
            ],
            [
              -0.30925,
              -0.29753,
              -0.28582,
              -0.26824,
              -0.23308,
              -0.18621,
              -0.15105,
              -0.11589,
              -0.0866,
              -0.06023
            ],
            [
              -0.37957,
              -0.36785,
              -0.35613,
              -0.33855,
              -0.30339,
              -0.25652,
              -0.2155,
              -0.18035,
              -0.15105,
              -0.12761
            ],
            [
              -0.43816,
              -0.43816,
              -0.41472,
              -0.403,
              -0.36785,
              -0.31511,
              -0.27996,
              -0.2448,
              -0.2155,
              -0.19207
            ]
          ]
        },
        "timing_type": "hold_rising"
      }
    ]
  },
  "statetable \"CLK GATE SCE\",\"M0\"": {
    "table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
  }
}