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| "cell_footprint": "dlxbp", |
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| "latch IQ,IQ_N": { |
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| "enable": "GATE" |
| }, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
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| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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| ] |
| }, |
| "pin GATE": { |
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| "clock": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_high": 0.63776, |
| "min_pulse_width_low": 0.63776, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
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