{
  "area": 23.976,
  "cell_footprint": "dlclkp",
  "cell_leakage_power": 0.0,
  "clock_gating_integrated_cell": "latch_posedge",
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.01216,
    "clock": "true",
    "clock_gate_clock_pin": "true",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
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          0.01735,
          0.02602,
          0.03903,
          0.05855,
          0.08782,
          0.13172,
          0.19757,
          0.29634,
          0.44449,
          0.6667,
          1.0,
          1.5
        ],
        "values": [
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          0.01469,
          0.0144,
          0.01433,
          0.01421,
          0.01416,
          0.01411,
          0.01402,
          0.01393,
          0.015,
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          0.01621,
          0.01651
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      },
      "rise_power hidden_pwr_template13": {
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          0.02602,
          0.03903,
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          0.13172,
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        "values": [
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          0.00888,
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          0.00927,
          0.00925,
          0.01003,
          0.01025
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      }
    },
    "max_transition": 1.0,
    "min_pulse_width_high": 0.39753,
    "min_pulse_width_low": 0.39753,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "pin GATE": {
    "capacitance": 0.00195,
    "clock": "false",
    "clock_gate_enable_pin": "true",
    "direction": "input",
    "internal_power": {
      "fall_power hidden_pwr_template13": {
        "index_1": [
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          0.02602,
          0.03903,
          0.05855,
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          0.13172,
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          0.29634,
          0.44449,
          0.6667,
          1.0,
          1.5
        ],
        "values": [
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          0.00211,
          0.00315,
          0.00255,
          0.00254,
          0.00253,
          0.00253,
          0.00254,
          0.00274,
          0.00274,
          0.00295,
          0.00295
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      },
      "rise_power hidden_pwr_template13": {
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          0.02602,
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          0.05855,
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          0.13172,
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          1.5
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        "values": [
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          0.00283,
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          0.00246,
          0.0025,
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          0.0027,
          0.00268,
          0.0029,
          0.0029
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      }
    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "timing": [
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            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
          ],
          "index_2": [
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "values": [
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              0.33475,
              0.28494,
              0.20584,
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              0.01541
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              0.15603,
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              0.06228,
              0.0242
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              0.22635,
              0.16775,
              0.11795,
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              0.23221,
              0.18533,
              0.14139,
              0.10623
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            [
              0.5574,
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              0.53982,
              0.51053,
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              0.3201,
              0.27029,
              0.22928,
              0.19119
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            [
              0.63943,
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              0.59256,
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              0.46365,
              0.40213,
              0.35232,
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              0.27029
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            [
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              0.47244,
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              0.3406
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              0.59842,
              0.54568,
              0.49881,
              0.46072
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "index_2": [
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "values": [
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              0.29959,
              0.27908,
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              0.22049,
              0.19705,
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              0.15896,
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              0.1531
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              0.16482
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              0.46072
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        "timing_type": "setup_rising"
      },
      {
        "fall_constraint sethold_template_fall10x10": {
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            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "index_2": [
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            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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          "values": [
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              0.02127,
              0.02713,
              0.04178,
              0.06814,
              0.11795,
              0.19705,
              0.25564,
              0.30545,
              0.34939,
              0.38748
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              0.01248,
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              0.03299,
              0.05936,
              0.10916,
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              0.24686,
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              -0.06662,
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              -0.15158,
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              0.0242,
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              0.1326,
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              -0.23361,
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              -0.18674,
              -0.13986,
              -0.06076,
              0.00076,
              0.05057,
              0.09451,
              0.1326
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              -0.30979,
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              -0.06955,
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              0.0242,
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              -0.37424,
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              -0.09299,
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        "related_pin": "CLK",
        "rise_constraint sethold_template_rise10x10": {
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            0.25,
            0.5,
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            1.0,
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          "index_2": [
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            0.25,
            0.5,
            0.75,
            1.0,
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            1.5
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          "values": [
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              0.07986,
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              0.1033,
              0.12381,
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              0.22635,
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              0.00076,
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              -0.07541,
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              -0.0344,
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        "timing_type": "hold_rising"
      }
    ]
  },
  "pin GCLK": {
    "clock_gate_out_pin": "true",
    "direction": "output",
    "internal_power": {
      "fall_power pwr_template13x17": {
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          1.0,
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        "index_2": [
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          0.06984,
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          0.1364,
          0.1705,
          0.21313,
          0.26641
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        "values": [
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      "related_pin": "CLK",
      "rise_transition delay_template13x17": {
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      "timing_sense": "positive_unate"
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  },
  "pin M0": {
    "direction": "internal",
    "internal_node": "M0",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR"
  },
  "statetable \"CLK GATE\",\"M0\"": {
    "table": "L L : - : L ,L H : - : H ,H - : - : N"
  }
}