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| "area": 14.3856, |
| "cell_footprint": "and4b", |
| "cell_leakage_power": 0.0, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin A_N": { |
| "capacitance": 0.00353, |
| "clock": "false", |
| "direction": "input", |
| "internal_power": { |
| "fall_power hidden_pwr_template13": { |
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| 0.03903, |
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| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin B": { |
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| "internal_power": { |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin C": { |
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| "clock": "false", |
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| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
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| }, |
| "pin D": { |
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| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin X": { |
| "direction": "output", |
| "function": "(!A_N&B&C&D)", |
| "internal_power": [ |
| { |
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| "related_pin": "A_N", |
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| "when": "(B&C&D)" |
| }, |
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