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| "cell_footprint": "sky130_fd_sc_lp__sdfxtp", | |
| "cell_leakage_power": 0.0, | |
| "ff,IQ,IQ_N": { | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)" | |
| }, | |
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| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
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| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
| "capacitance": 0.00213, | |
| "clock": "true", | |
| "direction": "input", | |
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| }, | |
| "max_transition": 1.0, | |
| "min_pulse_width_high": 0.73151, | |
| "min_pulse_width_low": 0.73151, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin,D": { | |
| "capacitance": 0.00225, | |
| "clock": "false", | |
| "direction": "input", | |
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| "related_pin": "CLK", | |
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| } | |
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| }, | |
| "pin,Q": { | |
| "direction": "output", | |
| "function": "IQ", | |
| "internal_power": { | |
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