{ | |
"area": 44.7552, | |
"cell_footprint": "sky130_fd_sc_lp__sdfrtp", | |
"cell_leakage_power": 0.0, | |
"ff,IQ,IQ_N": { | |
"clear": "!RESET_B", | |
"clocked_on": "CLK", | |
"next_state": "(D&!SCE) | (SCD&SCE)" | |
}, | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
"capacitance": 0.00198, | |
"clock": "true", | |
"direction": "input", | |
"internal_power": { | |
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"min_pulse_width_low": 0.93073, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR" | |
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"pin,D": { | |
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"clock": "false", | |
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"nextstate_type": "data", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
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