| { |
| "area": 23.976, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01335, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| "min_pulse_width_low": 0.64948, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
| "max_transition": 1.0, |
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| "timing_type": "setup_rising" |
| }, |
| { |
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| "related_pin": "CLK", |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.45317, |
| 0.53327, |
| 0.63023, |
| 0.74735, |
| 0.88698, |
| 1.05494, |
| 1.25705, |
| 1.50199 |
| ], |
| [ |
| 0.05647, |
| 0.28405, |
| 0.32997, |
| 0.38547, |
| 0.45281, |
| 0.53328, |
| 0.63074, |
| 0.74787, |
| 0.8881, |
| 1.05646, |
| 1.25877, |
| 1.50243 |
| ], |
| [ |
| 0.05646, |
| 0.28412, |
| 0.33027, |
| 0.38608, |
| 0.45373, |
| 0.5338, |
| 0.63081, |
| 0.74714, |
| 0.88737, |
| 1.05634, |
| 1.25915, |
| 1.50161 |
| ], |
| [ |
| 0.05646, |
| 0.28372, |
| 0.33048, |
| 0.38557, |
| 0.45277, |
| 0.53352, |
| 0.63019, |
| 0.74732, |
| 0.88716, |
| 1.05493, |
| 1.25925, |
| 1.50059 |
| ], |
| [ |
| 0.05648, |
| 0.28374, |
| 0.33036, |
| 0.38531, |
| 0.4536, |
| 0.53352, |
| 0.6301, |
| 0.74723, |
| 0.88707, |
| 1.05544, |
| 1.25937, |
| 1.5 |
| ], |
| [ |
| 0.05649, |
| 0.28445, |
| 0.33021, |
| 0.38583, |
| 0.4535, |
| 0.53362, |
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| 0.74678, |
| 0.88691, |
| 1.05478, |
| 1.2591, |
| 1.50083 |
| ], |
| [ |
| 0.05651, |
| 0.28396, |
| 0.33016, |
| 0.38569, |
| 0.45374, |
| 0.53386, |
| 0.63086, |
| 0.74737, |
| 0.88758, |
| 1.05533, |
| 1.25915, |
| 1.50138 |
| ], |
| [ |
| 0.05649, |
| 0.28408, |
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| 0.38611, |
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| 0.53401, |
| 0.63095, |
| 0.74721, |
| 0.88759, |
| 1.0554, |
| 1.25788, |
| 1.50231 |
| ], |
| [ |
| 0.05675, |
| 0.28416, |
| 0.33089, |
| 0.38621, |
| 0.45283, |
| 0.53341, |
| 0.63098, |
| 0.74757, |
| 0.88738, |
| 1.05644, |
| 1.25927, |
| 1.49955 |
| ], |
| [ |
| 0.05865, |
| 0.28473, |
| 0.3307, |
| 0.38703, |
| 0.4536, |
| 0.53425, |
| 0.6317, |
| 0.74776, |
| 0.88777, |
| 1.0561, |
| 1.2593, |
| 1.5019 |
| ], |
| [ |
| 0.0616, |
| 0.2866, |
| 0.3327, |
| 0.3881, |
| 0.4543, |
| 0.5346, |
| 0.6314, |
| 0.7474, |
| 0.8878, |
| 1.0562, |
| 1.2578, |
| 1.5019 |
| ], |
| [ |
| 0.0659, |
| 0.2892, |
| 0.335, |
| 0.3899, |
| 0.4572, |
| 0.537, |
| 0.6333, |
| 0.7492, |
| 0.8889, |
| 1.0564, |
| 1.2579, |
| 1.5017 |
| ], |
| [ |
| 0.0724, |
| 0.2919, |
| 0.3373, |
| 0.3921, |
| 0.4586, |
| 0.5384, |
| 0.6349, |
| 0.751, |
| 0.8908, |
| 1.0582, |
| 1.2587, |
| 1.5008 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
