| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01229, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.47956, |
| "min_pulse_width_low": 0.47956, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00185, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.75, |
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| 0.51477, |
| 0.47375 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.125, |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x22": { |
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| 0.11572, |
| 0.13107, |
| 0.14939, |
| 0.17136, |
| 0.19823, |
| 0.2306, |
| 0.26932, |
| 0.3165, |
| 0.37273, |
| 0.44088, |
| 0.52355, |
| 0.62103, |
| 0.74079, |
| 0.88342, |
| 1.05081, |
| 1.26073, |
| 1.50223 |
| ], |
| [ |
| 0.03875, |
| 0.07715, |
| 0.08452, |
| 0.09332, |
| 0.10373, |
| 0.11635, |
| 0.13145, |
| 0.14982, |
| 0.17162, |
| 0.19843, |
| 0.23027, |
| 0.2693, |
| 0.31615, |
| 0.37266, |
| 0.44142, |
| 0.52267, |
| 0.62214, |
| 0.73959, |
| 0.88281, |
| 1.053, |
| 1.2574, |
| 1.5045 |
| ], |
| [ |
| 0.04122, |
| 0.0796, |
| 0.087, |
| 0.0957, |
| 0.106, |
| 0.1185, |
| 0.1335, |
| 0.1516, |
| 0.1734, |
| 0.1997, |
| 0.2316, |
| 0.2703, |
| 0.3169, |
| 0.3733, |
| 0.4412, |
| 0.5232, |
| 0.6222, |
| 0.74, |
| 0.8828, |
| 1.0534, |
| 1.2585, |
| 1.5047 |
| ], |
| [ |
| 0.0445, |
| 0.083, |
| 0.0902, |
| 0.0988, |
| 0.1091, |
| 0.1215, |
| 0.1364, |
| 0.1543, |
| 0.176, |
| 0.202, |
| 0.2337, |
| 0.2718, |
| 0.3182, |
| 0.3741, |
| 0.442, |
| 0.5239, |
| 0.6224, |
| 0.74, |
| 0.8832, |
| 1.0541, |
| 1.2581, |
| 1.5025 |
| ], |
| [ |
| 0.0497, |
| 0.0878, |
| 0.0949, |
| 0.1034, |
| 0.1135, |
| 0.1257, |
| 0.1402, |
| 0.158, |
| 0.1792, |
| 0.2052, |
| 0.2364, |
| 0.2745, |
| 0.3209, |
| 0.377, |
| 0.4437, |
| 0.5244, |
| 0.6223, |
| 0.7406, |
| 0.8826, |
| 1.0531, |
| 1.2574, |
| 1.5049 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
