| { |
| "area": 23.976, |
| "cell_footprint": "sky130_fd_sc_lp__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "dont_use": "true", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01213, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.4444, |
| "min_pulse_width_low": 0.4444, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00191, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| ], |
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| 0.0023, |
| 0.0023, |
| 0.00229, |
| 0.0023, |
| 0.00248, |
| 0.00249, |
| 0.00268, |
| 0.00268 |
| ] |
| }, |
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| ], |
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| 0.00245, |
| 0.00266, |
| 0.00266 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.66926, |
| 0.61653, |
| 0.56379 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| 0.33235, |
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| 0.14192, |
| 0.12141 |
| ], |
| [ |
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| ], |
| [ |
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| ], |
| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.59309, |
| 0.55793, |
| 0.5345, |
| 0.50813 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| 0.39094, |
| 0.44075 |
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| [ |
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| 0.32649, |
| 0.38215, |
| 0.42903 |
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| [ |
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| 0.3675, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.22722, |
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| -0.12175 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ], |
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| 0.27375, |
| 0.29719, |
| 0.3177 |
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| [ |
| 0.08918, |
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| 0.2386, |
| 0.26497, |
| 0.2884, |
| 0.30891 |
| ], |
| [ |
| 0.07747, |
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| [ |
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| [ |
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| 0.2093, |
| 0.23274 |
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| [ |
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| [ |
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| 0.01008, |
| 0.03938, |
| 0.06282, |
| 0.08625 |
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| [ |
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| [ |
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| [ |
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| -0.06902 |
| ] |
| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x20": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
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| 0.03903, |
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| 0.44449, |
| 0.6667, |
| 1.0, |
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| "index_2": [ |
| 0.0, |
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| 0.16651, |
| 0.19981, |
| 0.23977 |
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| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
