blob: 5014819c9d955afc02e05442b02ff1750b7470db [file] [log] [blame]
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog primitive definition.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`ifdef NO_PRIMITIVES
`include "./sky130_fd_sc_lp__udp_dlatch_p.blackbox.v"
`else
primitive sky130_fd_sc_lp__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
reg Q;
table
// D GATE : Qt : Qt+1
? 0 : ? : - ; // clock disabled
0 1 : ? : 0 ; // clock enabled
1 1 : ? : 1 ; // transparent data
1 x : 1 : 1 ; // Reducing pessimism.
0 x : 0 : 0 ;
endtable
endprimitive
`endif // NO_PRIMITIVES
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_V