)]}'
{
  "commit": "17bc8e605cd035a6745722530fe3ac369f310022",
  "tree": "f95106898be151c1c074ec9cf6ce084f7fc1d0b8",
  "parents": [
    "7dbbc58075ddaa96cc015f3b0f3fc886363729a3",
    "075cfd7bbb090dc7b463be90425e039b66498687"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:09:08 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:09:08 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}