| { |
| "area": 44.9328, |
| "cell_footprint": "sky130_fd_sc_hvl__sdlclkp", |
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| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
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| "driver_waveform_rise": "ramp", |
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| { |
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| { |
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| { |
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| { |
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| { |
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| { |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
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| "clock_gate_clock_pin": "true", |
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