| { |
| "area": 60.5616, |
| "cell_footprint": "sky130_fd_sc_hvl__sdfxtp", |
| "cell_leakage_power": 16.11776, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 13.2234499, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 13.0772433, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 18.6135587, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 14.3191992, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 20.0968948, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 15.6653233, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 18.6524751, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 19.4707717, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 12.8633699, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 15.9317324, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 15.9053286, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 13.1856819, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 15.7591717, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 16.4838951, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 18.9634939, |
| "when": "!D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 15.6725566, |
| "when": "D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002571, |
| "clock": "true", |
| "direction": "input", |
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| 0.013, |
| 0.026, |
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| 1.9936274 |
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| }, |
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| "min_pulse_width_low": 0.311545, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin,D": { |
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| "clock": "false", |
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| "internal_power": { |
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| 0.853147 |
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| }, |
| "max_transition": 3.75, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| { |
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| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_11_11_1": { |
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| } |
| } |
