tree 1c6cb8ae3e9d5f1825e68d29c2b144db175bf0da
parent c54a9afeeb0a1ed1805569e94e14d0eacd3e4580
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>