)]}'
{
  "commit": "e16912f6328429ac8ad9b88857be6ccd9291f698",
  "tree": "1c6cb8ae3e9d5f1825e68d29c2b144db175bf0da",
  "parents": [
    "c54a9afeeb0a1ed1805569e94e14d0eacd3e4580"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e6360771ad8f124e4f171912cb460506734737b9",
      "old_mode": 33188,
      "old_path": "models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v",
      "new_id": "3e8b262dd45240d73934e923532d23828ccc826c",
      "new_mode": 33188,
      "new_path": "models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v"
    },
    {
      "type": "modify",
      "old_id": "6579adc21e1caab36224675f9b668d00f32990ff",
      "old_mode": 33188,
      "old_path": "models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v",
      "new_id": "764d1c1e0e52fe0a93bac09955992b629111acd8",
      "new_mode": 33188,
      "new_path": "models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.v"
    }
  ]
}