tree e0c025ea02ef6a9ff7e7cce1133540557a1dd3ce
parent f604d5b734086bac04177577e3f07b4962efc29e
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>