)]}'
{
  "commit": "bf24011c437604adfa80dc20182fd5e9920c3861",
  "tree": "56c37a7c13857f50af27094b2c9aad3656b93d31",
  "parents": [
    "92e148f7e636cf3414a38f3abb51c757bfb48bdc",
    "916398a7d88e49e511b9148963de21d726680de2"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing include path.\n\nThe include lines previously had,\n`include \"sky130_fd_sc_hd__o221a.pp.functional.v\"`\nbut the actual filename is\n`include \"sky130_fd_sc_hd__o221a.functional.pp.v\"`.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}