tree 3a26ac8e255151161b9b8adc59bcc29eaa25dd67
parent 916398a7d88e49e511b9148963de21d726680de2
parent c54a9afeeb0a1ed1805569e94e14d0eacd3e4580
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing usage of cell reserved word.

`cell` is a Verilog reserved word.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>