)]}'
{
  "commit": "a94c8163a66304bd2b850537739392ad27ba388b",
  "tree": "3a26ac8e255151161b9b8adc59bcc29eaa25dd67",
  "parents": [
    "916398a7d88e49e511b9148963de21d726680de2",
    "c54a9afeeb0a1ed1805569e94e14d0eacd3e4580"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}