)]}'
{
  "commit": "92e78fb5e96de314374fb2ef54ab4b1fef628817",
  "tree": "6fe3baa3feafd6dac48c7fab2dbf6b951ceeb684",
  "parents": [
    "816a15783e0751d784bcd504915c0019ac56b8f3",
    "52f30ef0ec41942bebd2ae8c9fc41ecd177762a7"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:07:56 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:07:56 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}