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  "area": 44.9328,
  "cell_footprint": "sky130_fd_sc_hvl__sdlclkp",
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  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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        "related_pin": "CLK",
        "rise_constraint,vio_11_11_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,vio_11_11_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}