| { |
| "area": 80.0976, |
| "cell_footprint": "sky130_fd_sc_hvl__sdfxbp", |
| "cell_leakage_power": 0.4681696, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.4325159, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.4985872, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.467996, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.4845344, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.4581647, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.4451048, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.4406782, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.4626112, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.4950452, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.4321257, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.4492949, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.5338267, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.4634698, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.5032357, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.4731124, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.4504099, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002459, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002386, |
| "internal_power": { |
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| "index_1": [ |
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| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
| 0.432, |
| 0.864, |
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| 2.5, |
| 3.125, |
| 3.7499999 |
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| 0.100431, |
| 0.1000907, |
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| 0.1139079, |
| 0.1280833, |
| 0.1459069, |
| 0.1955832, |
| 0.2213699, |
| 0.2471567 |
| ] |
| }, |
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| 0.1516026, |
| 0.1769983, |
| 0.2023941 |
| ] |
| } |
| }, |
| "max_transition": 3.75, |
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| "min_pulse_width_low": 0.573016, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002531 |
| }, |
| "pin,D": { |
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| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002181, |
| "internal_power": { |
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| 0.013, |
| 0.026, |
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| 0.0568006, |
| 0.0798655, |
| 0.0918382, |
| 0.1038108 |
| ] |
| }, |
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| 0.058045, |
| 0.0696043, |
| 0.0811636 |
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| } |
| }, |
| "max_transition": 3.75, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002454, |
| "timing": [ |
| { |
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| 1.3024556, |
| 1.4920715, |
| 1.6780254 |
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| ] |
| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_11_11_1": { |
| "index_1": [ |
| 0.001, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_11_11_1": { |
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| 0.001, |
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| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
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| "pin,D": { |
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| "pin,Q": { |
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| "pin,Q_N": { |
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| "function": "IQ_N", |
| "signal_type": "test_scan_out_inverted" |
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| "pin,SCD": { |
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| "pin,SCE": { |
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| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
