| { |
| "area": 60.5616, |
| "cell_footprint": "sky130_fd_sc_hvl__sdfxtp", |
| "cell_leakage_power": 0.3544536, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.3275474, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.3851362, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.3563628, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.3290476, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.3601938, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.3601522, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.3606974, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.3563304, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.3563749, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.3251867, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.3275474, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.3866364, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.3607405, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.357863, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.3607419, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.3606988, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002487, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002407, |
| "internal_power": { |
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| 0.013, |
| 0.026, |
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| 0.216, |
| 0.432, |
| 0.864, |
| 1.296, |
| 2.5, |
| 3.125, |
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| "values": [ |
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| 0.189522, |
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| 0.3510919, |
| 0.4466787, |
| 0.7130836, |
| 0.8513749, |
| 0.9896662 |
| ] |
| }, |
| "rise_power,hidden_pwr_template11": { |
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| 0.013, |
| 0.026, |
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| 0.216, |
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| "values": [ |
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| 0.6534363, |
| 0.7919527, |
| 0.9304688 |
| ] |
| } |
| }, |
| "max_transition": 3.75, |
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| "min_pulse_width_low": 0.281882, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002567 |
| }, |
| "pin,D": { |
| "capacitance": 0.002443, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002337, |
| "internal_power": { |
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| 0.013, |
| 0.026, |
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| 0.3099935, |
| 0.3761561, |
| 0.4423186 |
| ] |
| }, |
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| 0.3242519, |
| 0.3901822 |
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| } |
| }, |
| "max_transition": 3.75, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00255, |
| "timing": [ |
| { |
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| [ |
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| 1.127895, |
| 1.35047, |
| 1.5657207 |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.013, |
| 0.026, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_11_11_1": { |
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| 0.001, |
| 0.013, |
| 0.026, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_11_11_1": { |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin,CLK": { |
| "direction": "input" |
| }, |
| "pin,D": { |
| "direction": "input" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
