)]}'
{
  "commit": "6dc60815830e2a6c26a4974475a782f2f94571d8",
  "tree": "54c27556d89619328f81c59fed7cfd057c4ed41c",
  "parents": [
    "bf24011c437604adfa80dc20182fd5e9920c3861",
    "a94c8163a66304bd2b850537739392ad27ba388b"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}