| { |
| "area": 60.5616, |
| "cell_footprint": "sky130_fd_sc_hvl__sdfxtp", |
| "cell_leakage_power": 0.03853961, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.0362617, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0392122, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0392134, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0388375, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0388485, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0388474, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0362622, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0414087, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0388348, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0358924, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 0.0362622, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0414082, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0388364, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0388343, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 0.0388364, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 0.0388375, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.001801, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001778, |
| "internal_power": { |
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| 0.576, |
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| 1.728, |
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| 0.0200665, |
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| 0.0200457, |
| 0.0200386 |
| ] |
| }, |
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| 1.728, |
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| 0.0147438 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 2.281366, |
| "min_pulse_width_low": 7.776651, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001824 |
| }, |
| "pin,D": { |
| "capacitance": 0.001974, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001959, |
| "internal_power": { |
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| 0.0065449, |
| 0.0065924, |
| 0.0066397 |
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| }, |
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| 0.001638, |
| 0.001623, |
| 0.001608 |
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| } |
| }, |
| "max_transition": 5.0, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00199, |
| "timing": [ |
| { |
| "clk_width": [ |
| 5.2e-08, |
| 2.6e-08 |
| ], |
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| [ |
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| [ |
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| [ |
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| 10.1340845, |
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| [ |
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| [ |
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| [ |
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| 7.6274612, |
| 8.1268643, |
| 8.616502 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| [ |
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| [ |
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| [ |
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| 2.8535625 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 2.6e-08, |
| "fall_constraint,vio_11_11_1": { |
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| }, |
| "related_pin": "CLK", |
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| } |
