| { |
| "area": 44.9328, |
| "cell_footprint": "sdlclkp", |
| "cell_leakage_power": 0.02671501, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0273617, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0251392, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0278022, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.029724, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 0.0251392, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0244319, |
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| }, |
| { |
| "value": 0.027061, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.027061, |
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| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
| "capacitance": 0.004048, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003959, |
| "internal_power": { |
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| 1.728, |
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| }, |
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| } |
| }, |
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| "min_pulse_width_low": 3.508649, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004138 |
| }, |
| "pin GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001684, |
| "internal_power": { |
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| 0.0192733 |
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| } |
| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001662, |
| "timing": [ |
| { |
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| }, |
| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_11_11_1": { |
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| }, |
| "pin M0": { |
| "direction": "internal", |
| "internal_node": "m0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin SCE": { |
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| "clock": "false", |
| "clock_gate_test_pin": "true", |
| "direction": "input", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "statetable \"CLK GATE SCE\",\"M0\"": { |
| "table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N" |
| } |
| } |
