{
  "area": 48.84,
  "cell_footprint": "dfxtp",
  "cell_leakage_power": 10.96557,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 9.4442001,
      "when": "D&!CLK"
    },
    {
      "value": 12.3640591,
      "when": "D&CLK"
    },
    {
      "value": 9.5136112,
      "when": "!D&!CLK"
    },
    {
      "value": 12.540414,
      "when": "!D&CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002027,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.001982,
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        "index_1": [
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          0.026,
          0.072,
          0.216,
          0.432,
          0.864,
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          3.7499999
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        "values": [
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      "rise_power hidden_pwr_template11": {
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          0.072,
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        "values": [
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    "max_transition": 3.75,
    "min_pulse_width_high": 1.424444,
    "min_pulse_width_low": 2.212153,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002072
  },
  "pin D": {
    "capacitance": 0.002057,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001915,
    "internal_power": {
      "fall_power hidden_pwr_template11": {
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        "values": [
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      "rise_power hidden_pwr_template11": {
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          0.072,
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          0.432,
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        "values": [
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    },
    "max_transition": 3.75,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.0022,
    "timing": [
      {
        "clk_width": 2.6e-08,
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        "related_pin": "CLK",
        "rise_constraint vio_11_11_1": {
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            0.026,
            0.072,
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            0.864,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_11_11_1": {
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            0.026,
            0.072,
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            0.864,
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          "values": [
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        "related_pin": "CLK",
        "rise_constraint vio_11_11_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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