{
  "area": 68.376,
  "cell_footprint": "dfrbp",
  "cell_leakage_power": 12.66108,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clear": "!RESET_B",
    "clocked_on": "CLK",
    "next_state": "D"
  },
  "leakage_power": [
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      "value": 16.484103,
      "when": "D&RESET_B&CLK"
    },
    {
      "value": 13.4359635,
      "when": "!D&RESET_B&!CLK"
    },
    {
      "value": 9.844074,
      "when": "!D&!RESET_B&CLK"
    },
    {
      "value": 16.1138658,
      "when": "!D&RESET_B&CLK"
    },
    {
      "value": 13.3127367,
      "when": "D&RESET_B&!CLK"
    },
    {
      "value": 11.1317782,
      "when": "D&!RESET_B&CLK"
    },
    {
      "value": 9.8391855,
      "when": "!D&!RESET_B&!CLK"
    },
    {
      "value": 11.1269332,
      "when": "D&!RESET_B&!CLK"
    }
  ],
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "pwell",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "nwell",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.00192,
    "clock": "true",
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    "fall_capacitance": 0.001877,
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          0.072,
          0.216,
          0.432,
          0.864,
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          3.125,
          3.7499999
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      "rise_power hidden_pwr_template11": {
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    "max_transition": 3.75,
    "min_pulse_width_high": 2.001219,
    "min_pulse_width_low": 2.70763,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001964
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  "pin D": {
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    "clock": "false",
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    "fall_capacitance": 0.001885,
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        "values": [
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      "rise_power hidden_pwr_template11": {
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        "values": [
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    "max_transition": 3.75,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001972,
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        "related_pin": "CLK",
        "rise_constraint vio_11_11_1": {
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            0.072,
            0.216,
            0.432,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "clk_width": 2.6e-08,
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          "values": [
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        "related_pin": "CLK",
        "rise_constraint vio_11_11_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
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}