)]}'
{
  "commit": "52f30ef0ec41942bebd2ae8c9fc41ecd177762a7",
  "tree": "5cbe38e4e57ae99d25e3c80b0c907eb98f03e541",
  "parents": [
    "95012feb0e766d60c1d8d8f9afbdde6cdb07006a",
    "85e478c47a81e6c401ddd277aceed83bddec7486"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:07:54 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:07:54 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}