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| [ |
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| [ |
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| 0.4024158, |
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| 0.7561867, |
| 1.1204968, |
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| [ |
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| 1.1188517, |
| 1.6720617, |
| 2.5030575, |
| 3.7427053 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_transition,delay_template11x12": { |
| "index_1": [ |
| 0.001, |
| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
| 0.432, |
| 0.864, |
| 1.296, |
| 2.5, |
| 3.125, |
| 3.75 |
| ], |
| "index_2": [ |
| 0, |
| 0.00941, |
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| ], |
| "values": [ |
| [ |
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| ], |
| [ |
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| [ |
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| [ |
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| [ |
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| 1.0868538, |
| 1.6239416, |
| 2.4251559, |
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| ], |
| [ |
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| 0.1327626, |
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| [ |
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| ], |
| [ |
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| [ |
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| [ |
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| [ |
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| 1.2121384, |
| 1.7323472, |
| 2.5019737, |
| 3.6738703 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
