| { |
| "area": 80.0976, |
| "cell_footprint": "sky130_fd_sc_hvl__sdfxbp", |
| "cell_leakage_power": 15.57356, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 16.7339707, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 13.9251091, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 16.6552603, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 13.9659218, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 18.4731412, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 19.3604777, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 15.6738764, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 14.9225663, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 14.5236552, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 14.5012251, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 16.1453428, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 15.5113504, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 13.0435778, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 15.1127288, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 14.8547628, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 15.7740612, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002001, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001963, |
| "internal_power": { |
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| 0.013, |
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| } |
| }, |
| "max_transition": 3.75, |
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| "min_pulse_width_low": 3.105329, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002039 |
| }, |
| "pin,D": { |
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| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001886, |
| "internal_power": { |
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| 0.0094419 |
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| }, |
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| 0.0045596 |
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| }, |
| "max_transition": 3.75, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002033, |
| "timing": [ |
| { |
| "clk_width": 2.6e-08, |
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| [ |
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| 3.3263814, |
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| 3.8240214 |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 2.6e-08, |
| "fall_constraint,vio_11_11_1": { |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_11_11_1": { |
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| 0.001, |
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| "pin,SCE": { |
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| } |
| } |
| } |
