| { |
| "area": 41.0256, |
| "cell_footprint": "dlclkp", |
| "cell_leakage_power": 0.01705329, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0161646, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 0.0182185, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 0.0176688, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 0.0161613, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
| "capacitance": 0.003993, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004045, |
| "internal_power": { |
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| } |
| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| }, |
| "pin GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001532, |
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| 0.0130906 |
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| } |
| }, |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001615, |
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| }, |
| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
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| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable \"CLK GATE\",\"M0\"": { |
| "table": "L L : - : L ,L H : - : H ,H - : - : N" |
| } |
| } |
