| { |
| "area": 41.0256, |
| "cell_footprint": "dlclkp", |
| "cell_leakage_power": 2.522098, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 2.7981568, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 2.7214959, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 2.3877675, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 2.1809712, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "pwell", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "nwell", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
| "capacitance": 0.005131, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.005005, |
| "internal_power": { |
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| 0.001, |
| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
| 0.432, |
| 0.864, |
| 1.296, |
| 2.5, |
| 3.125, |
| 3.7499999 |
| ], |
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| 0.0851661, |
| 0.086314, |
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| 0.0957898, |
| 0.1014333, |
| 0.1171709, |
| 0.1253379, |
| 0.1335049 |
| ] |
| }, |
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| 0.026, |
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| 0.0249888, |
| 0.0406637, |
| 0.0487984, |
| 0.0569331 |
| ] |
| } |
| }, |
| "max_transition": 3.75, |
| "min_pulse_width_low": 0.495991, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.005259 |
| }, |
| "pin GATE": { |
| "capacitance": 0.002073, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.00206, |
| "internal_power": { |
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| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
| 0.432, |
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| 2.5, |
| 3.125, |
| 3.7499999 |
| ], |
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| 0.0791265, |
| 0.0830023, |
| 0.0874797, |
| 0.0999666, |
| 0.1064464, |
| 0.1129261 |
| ] |
| }, |
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| 0.0393395, |
| 0.0436386, |
| 0.0556286, |
| 0.0618505, |
| 0.0680723 |
| ] |
| } |
| }, |
| "max_transition": 3.75, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002087, |
| "timing": [ |
| { |
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| [ |
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| [ |
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| 0.0764629 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_11_11_1": { |
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| 0.013, |
| 0.026, |
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| [ |
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| 1.1152812 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.001, |
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| 0.026, |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_11_11_1": { |
| "index_1": [ |
| 0.001, |
| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_transition delay_template11x11": { |
| "index_1": [ |
| 0.001, |
| 0.013, |
| 0.026, |
| 0.072, |
| 0.216, |
| 0.432, |
| 0.864, |
| 1.296, |
| 2.5, |
| 3.125, |
| 3.75 |
| ], |
| "index_2": [ |
| 0, |
| 0.00679, |
| 0.01018, |
| 0.01527, |
| 0.02291, |
| 0.03436, |
| 0.05154, |
| 0.07731, |
| 0.11596, |
| 0.17394, |
| 0.26091 |
| ], |
| "values": [ |
| [ |
| 0.0815842, |
| 0.1813878, |
| 0.2252763, |
| 0.2886363, |
| 0.3855218, |
| 0.5321703, |
| 0.7597011, |
| 1.1038297, |
| 1.6529621, |
| 2.4653344, |
| 3.6234822 |
| ], |
| [ |
| 0.08175, |
| 0.1817767, |
| 0.2254605, |
| 0.2883958, |
| 0.3857414, |
| 0.5334931, |
| 0.7566878, |
| 1.1066513, |
| 1.6538981, |
| 2.4628033, |
| 3.6292356 |
| ], |
| [ |
| 0.0817388, |
| 0.1818573, |
| 0.225392, |
| 0.2891849, |
| 0.3856616, |
| 0.5327277, |
| 0.7601631, |
| 1.1041743, |
| 1.6534137, |
| 2.4640625, |
| 3.6278016 |
| ], |
| [ |
| 0.0817507, |
| 0.1820881, |
| 0.225591, |
| 0.2888603, |
| 0.3847248, |
| 0.5335444, |
| 0.7599493, |
| 1.1049659, |
| 1.6347539, |
| 2.4646007, |
| 3.6319443 |
| ], |
| [ |
| 0.0817212, |
| 0.1820611, |
| 0.2256934, |
| 0.2891662, |
| 0.384941, |
| 0.5329166, |
| 0.7600353, |
| 1.1062405, |
| 1.6326979, |
| 2.463322, |
| 3.6315935 |
| ], |
| [ |
| 0.0840454, |
| 0.1843143, |
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| 0.2908725, |
| 0.3870907, |
| 0.5344034, |
| 0.7579277, |
| 1.1077035, |
| 1.6351926, |
| 2.4644276, |
| 3.6320447 |
| ], |
| [ |
| 0.0961283, |
| 0.1958298, |
| 0.2406158, |
| 0.3043327, |
| 0.3984338, |
| 0.5391387, |
| 0.763099, |
| 1.1087085, |
| 1.6358734, |
| 2.4326086, |
| 3.6422099 |
| ], |
| [ |
| 0.1050312, |
| 0.2055599, |
| 0.2487433, |
| 0.3119631, |
| 0.4051069, |
| 0.5526108, |
| 0.7759131, |
| 1.1132707, |
| 1.6523543, |
| 2.4323572, |
| 3.6485999 |
| ], |
| [ |
| 0.1308254, |
| 0.2320998, |
| 0.2757043, |
| 0.3371808, |
| 0.4278263, |
| 0.566218, |
| 0.7830188, |
| 1.1196618, |
| 1.6497271, |
| 2.4289413, |
| 3.6576031 |
| ], |
| [ |
| 0.142635, |
| 0.2454557, |
| 0.2896867, |
| 0.351539, |
| 0.4424301, |
| 0.5788786, |
| 0.7927966, |
| 1.1304474, |
| 1.6476289, |
| 2.4456668, |
| 3.6623271 |
| ], |
| [ |
| 0.1544581, |
| 0.2583654, |
| 0.3028414, |
| 0.3659447, |
| 0.4558722, |
| 0.5913847, |
| 0.8018554, |
| 1.1318407, |
| 1.6415906, |
| 2.4341678, |
| 3.6295769 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable \"CLK GATE\",\"M0\"": { |
| "table": "L L : - : L ,L H : - : H ,H - : - : N" |
| } |
| } |
