)]}'
{
  "commit": "d1e4650c36a3af1b266103a9aca26a0ec004cf53",
  "tree": "6281cdf2a48ac99d8e1cd13dda201560e704fee3",
  "parents": [
    "1d151b8713474e01b9d74b266007b6598ef6db83",
    "a13469d261b5272363c02fef366af22477f2d081"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}